1. Field of the Invention
The present invention relates generally to the design of processors within computing systems. More specifically, the present invention relates to a method and an apparatus that provides a fast-scanning operation for control-transfer instructions (CTIs) to speed up the process of forming of fetch bundles within an instruction fetch unit (IFU) of a processor.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in processor clock speeds. These increasing clock speeds have significantly increased processor performance. However, as clocks speeds continue to increase, the time available to perform computational operations during each pipeline stage decreases. This makes it harder to complete many types of computational operations within a single pipeline stage.
For example, as clock speeds continue to increase, it is becoming progressively harder to perform CTI-scanning operations within an instruction-fetch unit (IFU) within a single clock cycle. In high-performance processors, the IFU typically sends multiple instructions to the instruction-issue unit (IIU) at the same time. In order to do so, the IFU first needs to determine which instructions should be sent to the IFU. This determination typically involves performing a CTI-scanning operation on a cache line containing the instructions to identify CTIs, such as branches, which can cause the execution flow to jump to another location. As clock speeds continue to increase, it is becoming harder to perform a CTI-scanning operation on an entire cache line within a single cycle. This problem can be solved by using two pipeline stages to perform the CTI-scanning operation. However, using a second pipeline stage for the CTI-scanning operation can reduce overall processor performance.
Hence, what is needed is a method and an apparatus for performing a CTI-scanning operation to generate instruction fetch bundles without using an additional pipeline stage.